Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its stored data for some extended period without the application of power. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Storing data in a flash memory cell can be accomplished by changing the threshold voltage of the cell, through programming or “writing” of charge storage nodes, such as floating gates or trapping layers or other physical phenomena. By defining two or more ranges of threshold voltages to correspond to individual data states, one or more bits of information may be stored on each cell. Examples are single level and multilevel memory cells.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a transfer line, often referred to as a bit line. In NAND flash architecture, a column (e.g., NAND string) of memory cells are coupled in series with only the first memory cell of the column coupled to a bit line.
In many modern flash memory device implementations, the host interface and erase block management routines additionally allow for the flash memory device to appear as a read/write mass storage device (e.g., a magnetic disk) to the host. One such approach is to conform the interface to the flash memory to a standard interface for a conventional magnetic hard disk drive allowing the flash memory device to appear as a block read/write mass storage device or disk. This approach has been codified by the Personal Computer Memory Card International Association (PCMCIA), Compact Flash (CF) and Multimedia Card (MMC) standardization committees, which have each promulgated a standard for supporting flash memory systems, which are sometimes referred to as flash memory “cards”, which can emulate a hard disk drive protocol. Other such protocols exist as are known to those skilled in that art.
A typical operation performed by a host (e.g., processor) is to boot load upon power-up or a reset of the host system. This boot operation typically involves loading boot (e.g., system initialization) data from a memory device coupled to the host. In some systems, this operation is set in motion by applying a continuous clock signal and driving an input of a memory device storing the boot data to a fixed state (e.g., logic level 0 or 1) for a particular number of clock cycles. In such a system, the signal being driven to the fixed state for the required amount of time along with the applied clock signal are interpreted by the memory device as an indication to output boot data. One issue that can result from this method is that noise may appear on the signal and might be interpreted as an indication to terminate the boot operation when it was not intended. This would result in a failed boot load attempt. Another issue is that some hosts may not be configured to drive the signal to a fixed state for the required amount of time. Thus, some memory devices may require a hardware change to be able to utilize the boot method described above.
Thus, for the reasons stated above, and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for additional and more robust methods of performing boot operations with a host coupled to one or more memory devices.